Core Cell Library
VIS 's core cell libraries contain a rich set of functionalities, including inverted input of combinational logic, single output flip-flop and latch, and options for multiple drive capability. This diversity allows designers to achieve both the highest possible performance and the greatest density in the same chip.

I/O Cell Library
A variety of drive strengths is provided in each standard I/O cell library. Besides standard I/O library, VIS also offers a variety special function I/O cells, such as USB, LVDS, HSTL, PCI-X,
etc.

Mixed-Signal Library
VIS has developed mixed-signal cells for applications with different design requirements, such as graphic, video, and communication.

	PLL Family : PLL is one of the essential IPs in most of the digital circuit designs. Its major functions include clock generator and clock deskew. The normal output frequency of PLL holds within the range of 50-400 MHz for 0.25um generation.
	A/D and D/A Family : Please contact your account manager for a complete list of ADC and DAC macros.

Embedded SRAM Library
Please contact your account manager for a complete list of SRAM macros.